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NCP5680
FILED1[7..0] Power Flash LED1 ILED register $03
B7
B6
B5
B4
B3
B2
B1
B0
mA
RESET
0
0
0
0
3200
0
1600
0
800
0
400
0
200
0
100
0
FILED2 [7..0] Power Flash LED2 ILED register $04
B7
B6
B5
B4
B3
B2
B1
B0
mA
RESET
0
0
0
0
3200
0
1600
0
800
0
400
0
200
0
100
0
TILED [7..0] Torch / Video / Picture View/ View Finder LED1 & LED2 register $06
B7
B6
B5
B4
B3
B2
B1
B0
mA
RESET
0
0
128
0
64
0
32
0
16
0
8
0
4
0
2
0
NOTE:
The 200 ms time out is automatically asserted when TILED is higher than 100 mA. The TILED current is maintained constant when
TILED is equal or lower than 100 mA.
FLDLY1[7..0] Power flash Delay #1 register $07
B7
B6
B5
B4
B3
B2
B1
B0
ms
RESET
256
0
128
0
64
0
32
0
16
0
8
0
4
0
2
0
NOTE:
Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLDLY2[7..0] Power flash Delay #2 register $08
B7
B6
B5
B4
B3
B2
B1
B0
ms
RESET
256
0
128
0
64
0
32
0
16
0
8
0
4
0
2
0
NOTE:
Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLWID1[7..0] Power flash LED1 width register $0A
B7
B6
B5
B4
B3
B2
B1
B0
ms
RESET
128
0
64
0
32
0
16
0
8
0
4
0
2
0
1
0
NOTE:
Tolerance of the Fpwr Clock parameter applies to the timing parameters.
FLWID2[7..0] Power flash LED2 width register $0B
B7
B6
B5
B4
B3
B2
B1
B0
ms
RESET
128
0
64
0
32
0
16
0
8
0
4
0
2
0
1
0
NOTE:
Tolerance of the Fpwr Clock parameter applies to the timing parameters.
PHSEN[7..0] Photo Sense Reference register $0D
B7
B6
B5
B4
B3
B2
B1
B0
mV
RESET
1280
0
640
0
320
0
160
0
80
0
40
0
20
0
10
0
NOTE:
a ± 12.5% tolerance applies to each bit of the PHSEN register
PHGAIN[7..0] Photo Sense Input Amplifier gain register $0E
B7
B6
B5
B4
B3
B2
B1
B0
gain
RESET
0
0
8
0
4
0
2
0
1
0
0.5
0
0.25
0
0.125
0
NOTE:
a ± 10% tolerance applies to each bit of the PHGAIN register
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